This syllabus is under construction! The content and links are subject to change.
An introductory course on the digital logic design. Topics include Boolean algebra, combinational and sequential logic design, finite state machines, memories, and case studies. Design methodology using hardware description languages and modern CAD tools is covered in the lab portion of the course.
Announcements
Schedule
| Day | Lecture Topic/Lab | Quiz | Lab | Project Deadlines |
|---|---|---|---|---|
| Week 1 Tue May 5 |
1. Course Overview | No Quiz | No Lab | Project 0 |
| Week 1 Wed May 6 |
2. Binary Numbers | Quiz 1 | Lab 1 | Project 1 - Due May 10 |
| Thu May 7 | 3. Boolean Algebra | Quiz 2 | ||
| Week 2a Mon May 11 |
4. Positive Binary Numbers | Quiz 3 | Lab 2 | |
| Tue May 12 | 5. Binary Arithmetic I | |||
| Week 2b Wed May 13 |
6. Binary Arithmetic II | Quiz 4 | Lab 3 | Project 2 - Due May 15 |
| Thu May 14 | 7. Combinational Blocks | |||
| Week 3a Mon May 18 |
8. Combinational Blocks Continued | Quiz 5 | Lab 4 | Project 3 - Due May 20 |
| Tue May 19 | 9. Two Level Logic Minimization | Quiz 6 | ||
| Week 3b Wed May 20 |
10. Timing and Delay | Quiz 7 | Lab 5 | |
| Thu May 21 | 11. Exam 1 - Review | Exam 1 (6-8pm) | ||
| Week 4a Mon May 25 |
Memorial Day Holiday | Lab 6 | ||
| Tue May 26 | 12. Latches and Flip-Flops | Quiz 8 | ||
| Week 4b Wed May 27 |
13. Sequential Circuits Analysis | Quiz 9 | Lab 7 | Project 4 - Due May 28 |
| Thu May 28 | 14. Sequential Circuit Design | Quiz 10 | ||
| Week 5a Mon Jun 1 |
15. Sequential Design Examples | Quiz 11 | Lab 8 | Project 5 - Due June 2 |
| Tue Jun 2 | 16. Sequential Building Blocks | Quiz 12 | ||
| Week 5b Wed Jun 3 |
17. Register Transfer Level (RTL) Design | Lab 9 | ||
| Thu Jun 4 | 18. Register Transfer Level (RTL) Design II | Quiz 13 | ||
| Week 6a Mon Jun 8 |
19. Sequential Timing Analysis | Quiz 14 | No Labs | |
| Tue Jun 9 | 20. Exam 2 - Review | Exam 2 (6-8pm) | ||
| Week 6b Wed Jun 10 |
21. Sequential Multiplication | Quiz 15 | Lab 10 | Project 6 - Due June 11 |
| Thu Jun 11 | 22. Project 7 Overview | |||
| Week 7a Mon Jun 15 |
23. Algorithmic Two-Level Logic Minimization | Lab 11 | Project 7 checkpoint - Due June 16 | |
| Tue Jun 16 | 24. Designing Fast Adders I | |||
| Week 7b Wed Jun 17 |
25. Designing Fast Adders II | Quiz 16 | Lab 12 | |
| Thu Jun 18 | 26. State Assignment and Minimization | Quiz 17 | ||
| Week 8a Mon Jun 22 |
No Class | No Labs | Project 7 - Due June 22 | |
| Final Exam: June 24, 2026, 4:00 PM - 6:00 PM | ||||
Projects
Project 0
Getting Started
Due: No Due Date - Do not submit
Project 1
Selector
Due: May 10, 2026
Project 2
Robot Control
Due: May 15, 2026
Project 3
Combinational Calculator
Due: May 20, 2026
Project 4
Timing and Delay
Due: May 28, 2026
Project 5
Up-Down Counter
Due: June 2, 2026
Project 6
Traffic Light Controller
Due: June 11, 2026
Project 7
Sequential Calculator
Due: June 20, 2026
Logistics
Recordings
Admin Requests
- Exam 1 ConflictReport a conflict and request alternate scheduling for the first exam.
- Exam 2 ConflictReport a conflict and request alternate scheduling for the second exam.
If there is something not on these forms, contact eecs270-s26@umich.edu.
Instructors
Platforms: Linux, Vim, Emacs, VS Code
Interests: swimming, running, skiing, coffee
Platforms: Mac, Linux, VS Code
Interests: croissant, black_nib, airplane
Platforms: Mac, Linux, VS Code
Interests: croissant, black_nib, airplane
Syllabus
EECS 270 introduces you to the exciting world of digital logic design. Digital devices have proliferated in the last quarter century and have become essential in just about anything we do or depend on in a modern society. Computers of all varieties are now at the heart of commerce, communications, education, health care, entertainment, defense, etc. Personal computers have become standard fixtures in most homes and schools. But while the computer is the most visible digital computing device, it is by no means the only one. Embedded digital controllers can be found in such diverse applications as automobiles, airplanes, elevators, cellphones, televisions, cameras, and many kitchen appliances, to name just a tiny few.
This course provides you with a basic understanding of what digital devices are, how they operate, and how they can be designed to perform useful functions. It forms the foundation for the more advanced hardware courses in our CS, CE, and EE curricula, notably EECS 373, 427, and 470. You will learn about digital design through a combination of lectures, labs, and projects. Through the projects, you will learn to apply the concepts learned in lecture to design real digital circuits using modern design tools and FPGAs.
Attendance Policy
In-person attendance is highly encouraged. If you must miss class for any reason, recordings of the lectures can be accessed through this link no later than a few hours after the lecture. Lectures cannot be attended remotely via Zoom. Lab sessions require attendance, and labs are graded.
Course Topics
- Bits Everywhere!
- Switching Functions
- Boolean Algebra
- Positive Binary Numbers
- Binary Arithmetic
- Combinational Blocks
- Latches and Flip-Flops
- Timing and Delay
- Sequential Circuit Analysis
- Sequential Circuit Design
- Two Level Logic Minimization
- Sequential Building Blocks
- Register Transfer Level (RTL) Design
- Sequential Timing Analysis
- Sequential Multiplication
- Algorithmic Two-Level Logic Minimization
- Designing Fast Adders
- State Assignment and Minimization
Projects
You will complete seven projects through the semester. In these projects, you will design and implement various digital circuits for deployment on the DE2-115 FPGA development board.
The projects increase in complexity as the semester progresses. The first four projects focus on combinational logic design, while the last three projects focus on sequential logic design. You will use Verilog as the hardware description language (HDL) for all projects.
For further details on the projects, please refer to the Projects Overview page.
Optional Textbooks
- F. Vahid, Digital Design with RTL Design, VHDL, and Verilog, 2nd ed., Wiley.
- J. F. Wakerly, Digital Design: Principles and Practices, 4th ed., Prentice-Hall.
- J. P. Hayes, Introduction to Digital Logic Design, Addison-Wesley.
- C. H. Roth, Jr., Fundamentals of Logic Design.
- R. H. Katz, Contemporary Logic Design, Prentice-Hall.
- D. Thomas, P. Moorby, The Verilog Hardware Description Language.
Grading
Your final grade will be determined based on the following components: The 5 lowest quizzes will be dropped from your final grade calculation. The 2 lowest lab grades will also be dropped.
| Component | Weight |
|---|---|
| Quizzes | 5% |
| Labs | 5% |
| Projects | 30% |
| Midterm 1 | 20% |
| Midterm 2 | 20% |
| Final Exam | 20% |
Your final letter grade will be determined based on your overall percentage in the course, according to the following scale:
| Percentage | Letter Grade |
|---|---|
| 100% - 95% | A+ |
| 95% - 85% | A |
| 85% - 81% | A- |
| 81% - 78% | B+ |
| 78% - 75% | B |
| 75% - 71% | B- |
| 71% - 68% | C+ |
| 68% - 65% | C |
| 65% - 60% | C- |
| 60% - 57% | D+ |
| 57% - 54% | D |
| 54% - 50% | D- |
| Below 50% | E |
Academic Integrity
We encourage collaboration in EECS 270, especially on concepts, tools, specifications, and strategies. However, all submitted work must be your own. If you are unsure about what constitutes collaboration versus copying, please ask a member of the teaching staff for clarification.
| Encouraged Collaboration | Unacceptable Collaboration |
|---|---|
| Sharing high-level design strategies, e.g., module organization | Walking through a design or module step-by-step, sharing pseudocode, sharing comments |
| Helping others understand the spec or project nuances | Providing your code as a reference |
| Helping someone debug | Debugging someone's code for them |
| Explaining a synthesis error to someone | Fixing a synthesis error for someone |
| Discussing test strategies | Sharing test code to verify someone else's design, even if test cases are not submitted |
| Brainstorming edge cases for testing | Discussing specifics about what tests exposed instructor bugs on the autograder |
| Using starter code provided with a project or based on examples shown in lecture | Copying code in whole or in part, even if the code is modified \n Writing original code for someone else, or paying someone to write your project |
| Sharing your code in a way that could be copied, e.g., sending code over email or taking a picture of code |
Code Reuse
Reusing code (your own or other students') from previous semesters is not permitted.
Publishing Code
Any code you write for this course must not be published in any way or form, including posting on public repositories (e.g., GitHub, GitLab) or personal websites.
Generative AI Policy
The use of generative AI tools is not permitted for writing code or completing assignments in this course.